1. Technical Field
The present invention relates to a correction circuit which corrects nonlinear distortion caused in the input/output characteristics for a D/A converter.
2. Background Art
FIG. 4 is a circuit diagram showing the configuration of a conventional voltage addition-type D/A converter 10. As shown in FIG. 4, the voltage addition-type D/A converter 10 is configured by a voltage generator 11 which generates voltages respectively corresponding to the values of bits D0 to D7 of an input digital signal, and a voltage adding unit 12 which generates an output signal OUT that is obtained by adding the voltages generated by the voltage generator 11. In the illustrated example, the voltage generator 11 is configured by eight inverters N0 to N7, the outputs of which are produced by level-inverting the bits D0 to D7 of the input digital signal. In the voltage adding unit 12, one ends of resistors Ri0 to Ri7 are connected to output ends of the inverters N0 to N7, respectively, and the other ends are commonly connected to one end of a resistor R1. In the example, the resistors Ri0 to Ri7 have the same resistance 12R which is sufficiently lower than that of the resistor R1, and the output resistances of the inverters N0 to N7 are sufficiently lower than those of the resistors Ri0 to Ri7. The other end of the resistor R1 is connected to an inverting input terminal (minus input terminal) of an operational amplifier 13, and a non-inverting input terminal (plus input terminal) is fixed to a reference level Vref. In the case where the power source voltage of the voltage addition-type D/A converter 10 is VCC, for example, the reference level Vref is VCC/2. A resistor R2 is connected between the output end of the operational amplifier 13 and the inverting input terminal, and the output signal of the operational amplifier 13 is the output signal OUT of the voltage addition-type D/A converter 10.
When the number of H-level bits among the bits D0 to D7 of the input digital signal is n, one ends of the n number of resistors among the eight resistors Ri0 to Ri7 are made L level (0 V), and those of the (8−n) number of resistors are made H level (VCC) by the inverters N0 to N7. In a situation where the resistance of the resistor R1 is sufficiently higher than the resistance of the resistors Ri0 to Ri7, little current flows through the resistor R1. Therefore, in a situation where the bits D0 to D3 are at L level, the one ends of the resistors Ri0 to Ri3 are connected to the power source VCC, the bits D4 to D7 are at H level, and the one ends of the resistors Ri4 to Ri7 are grounded (the state of n=4), for example, the currents which flow from the power source VCC to the four parallel connected resistors Ri0 to Ri3 flow as they are through the four parallel connected resistors Ri4 to Ri7. Therefore, the voltage V1 of the common junctions of the resistors Ri0 to Ri7 and the resistor R1 is proportional to the number n of H-level bits among the bits D0 to D7 as indicated by the following expression:
                                                                        V                ⁢                                                                  ⁢                1                            =                              VCC                ⁢                                                      {                                          12                      ⁢                                              R                        /                                                  (                                                      8                            -                            n                                                    )                                                                                      }                                    /                                      {                                                                  (                                                  12                          ⁢                                                      R                            /                                                          (                                                              8                                -                                n                                                            )                                                                                                      )                                            +                                              (                                                  12                          ⁢                                                      R                            /                            n                                                                          )                                                              }                                                                                                                          =                              VCC                ·                                  n                  /                  8                                                                                        (        1        )            
The voltage V1 is multiplied by a factor of −R2/R1 by a multiplier configured by the resistors R1, R2 and the operational amplifier 13, and set as the output signal OUT. As described above, according to the voltage addition-type D/A converter 10, the output signal OUT, the voltage of which is proportional to the number n of H-level bits among the bits D0 to D7 of the input digital signal, and can express nine scales. A voltage addition-type D/A converter of this kind is disclosed in, for example, FIG. 5 of JP-2008-236010A.
In the above-described conventional voltage addition-type D/A converter 10, high- and low-potential power source lines 15, 16 which supply the power source voltage VCC to the voltage addition-type D/A converter 10 have wiring resistances Rp, Rn, respectively. In the conventional voltage addition-type D/A converter 10, depending on the contents of the bits D0 to D7 of the input digital signal, currents flowing through the wiring resistances Rp, Rn are different from each other. This will be specifically described below.
First, FIGS. 5A to 5C show equivalent circuits of the input side of the resistor R1 in FIG. 4 in the case where the values of the bits of the input digital signal are variously changed. In FIG. 5A, all of the bits D0 to D7 of the input digital signal are at L level, and, in FIG. 5B, all of the bits D0 to D7 of the input digital signal are at H level. In these cases, the resistors Ri0 to Ri7 are connected between the wiring resistance Rp on the side of the power source VCC and the resistor R1 or the wiring resistance Rn on the side of the ground and the resistor R1. Therefore, no current flows through the resistors Ri0 to Ri7, and no current flows also through the wiring resistances Rp, Rn. By contrast, in the case where, as shown in FIG. 5C, the bits D0 to D3 are at L level, and the bits D4 to D7 are at H level, a parallel connection of the four resistors Ri0 to Ri3 (the resistance 12R/4=3R) is connected between the wiring resistance Rp on the side of the power source VCC and the resistor R1, and that of the four resistors Ri4 to Ri7 (the resistance 12R/4=3R) is connected between the wiring resistance Rn on the side of the ground and the resistor R1. Therefore, a current of VCC/(6R) flows through the wiring resistances Rp, Rn.
Although the illustration is omitted, in the case where the number n of H-level bits among the bits D0 to D7 is other than 4, the current I flowing through the wiring resistances Rp, Rn is changed depending on the number n. Specifically, the relationships among the number n, the resistance Ra of the resistor between the wiring resistance Rp and the resistor R1, the resistance Rb of the resistor between the wiring resistance Rn and the resistor R1, and the current I flowing through the wiring resistances Rp, Rn are as listed below.
TABLE 1nRaRbI03R/2∞0112R/712R(7VCC)/(96R)22R6RVCC/(8R)312R/54R(5VCC)/(32R)43R3RVCC/(6R)54R12R/5(5VCC)/(32R)66R2RVCC/(8R)712R12R/7(7VCC)/(96R)8∞3R/20
As described above, in the conventional voltage addition-type D/A converter 10, the current I flowing through the wiring resistance Rp of the high-potential power source line 15 and the wiring resistance Rn of the low-potential power source line 16 is changed depending on the contents of the bits D0 to D7 of the input digital signal, and hence the power source voltage which is applied to the voltage generator 11 through the high- and low-potential power source lines 15, 16 is changed depending on the contents of the bits D0 to D7 of the input digital signal. In the conventional voltage addition-type D/A converter 10, in the case where the wiring resistance Rp of the high-potential power source line 15 and the wiring resistance Rn of the low-potential power source line 16 are high, therefore, there is a problem in that the linearity of the output signal OUT with respect to the input digital signal is degraded.